The present invention relates to a technique to set a design margin to be employed, in design of an ASIC (Application Specific IC), a system LSI or the like, for taking performance variation derived from variation in the fabrication process into consideration.
Recently, since transistors are rapidly improved in the refinement and the degree of integration in accordance with the development of fabrication technique, a variety of functions can be realized on one chip of a CMIS (Complementary Metal Insulator Semiconductor) integrated circuit (hereinafter referred to as the LSI). In the development of such an LSI, a design margin is generally provided. Factors to be considered in setting the design margin include, as factors that affect the circuit characteristics, not only the voltage and the temperature corresponding to the operation circumstances of the circuit but also variation or fluctuation occurring in the fabrication. Signal propagation delay caused by the variation or fluctuation occurring in the fabrication of an LSI will now be described with reference to FIG. 19.
FIG. 19 is a circuit diagram of a logic circuit, which is included in an ASIC, a system LSI or the like, decomposed into a plurality of signal paths.
As shown in FIG. 19, a signal path of a logic circuit 1 included in an ASIC, a system LSI or the like can be generally decomposed into a signal path 4 in which N (wherein N is a natural number) stages of circuit cells (that is, first through Nth circuit cells) 3 provided between, for example, a pair of flip-flops 2. Each of the N stages of circuit cells 3 is generally composed of a logic circuit element such as an inverter, a NAND or a NOR. Also, the N stages of circuit cells 3 each composed of an inverter or the like are connected to one another through the signal path 4. In designing such a logic circuit 1, a signal propagation delay time (hereinafter simply referred to as the delay time) caused through the propagation of a signal through the N stages of circuit cells 3 connected by the signal path 4 should be within a given time determined on the basis of a cycle time of a clock signal input to the logic circuit 1 (in most cases, on the basis of a reciprocal of the operation frequency or the clock frequency, or a cycle obtained by multiplying such a reciprocal by an integer). This relationship is represented by the following formula (1):
      Formula    ⁢                  ⁢          (      1      )        :          ⁢            t      cycle        ≥                            ∑                      i            =            1                    N                ⁢                  t          i                    +              t        others            wherein tcycle indicates the upper limit of the delay time required in the design of the logic circuit 1; ti indicates a time by which a signal input to the ith circuit cell out of the N stages of circuit cells 3 is delayed before being output (i.e., a delay time); Σti indicates the sum of signal propagation delay times ti caused in the respective circuit cells provided between the pair of flip-flops 2; and tothers indicates the sum of set-up times of the pair of flip-flops 2 and the skew of the clock signal.
In general, the design margin is set in consideration of the above-described delay time and hence is represented by the following formula (2) by using coefficients P, V and T designated as derating factors indicating, in the form of coefficients, various delay varying factors for delaying the propagation of a signal:tworst=ttyp×Pworst×Vworst×Tworst  Formula (2):wherein tworst is the worst value of the delay time Σti; ttyp is a standard value of the delay time Σti; P is a derating factor indicating, in the form of a coefficient, fabrication variation as the delay varying factor; V is a derating factor indicating, in the form of a coefficient, a power voltage range as the delay varying factor; and T is a derating factor indicating, in the form of a coefficient, a temperature range as the delay varying factor.
In using such derating factors, the standard value ttyp of the delay time Σti is first obtained, and the worst value of the delay time obtained under the worst conditions can be easily estimated as a value obtained by multiplying the standard value ttyp by the worst values of the respective derating factors. As a result, the logic circuit can be designed in a labor-saving manner. The specific values of the derating factors are listed in FIG. 20.
FIG. 20 is a diagram for showing the best values (in the column of “best”), the standard values (in the column of “typ”) and the worst values (in the column of “worst”) of the derating factors P, V and T used in the formula (2).
As shown in FIG. 20, each derating factor P, V or T has the best value, the standard value and the worst value. Among these values, the best value and the worst value are determined by assuming the standard value as 1. When the worst values of these derating factors are substituted in the formula (2), the worst value tworst of the delay time can be calculated in accordance with the following formula (3). On the other hand, the best value tbest of the delay time can be similarly calculated in accordance with the following formula (4). Under conditions where the signal propagation is delayed by times corresponding to the best value tbest and the worst value tworst of the delay time thus calculated, the operation of the LSI is checked at the time of the circuit design.tworst=ttyp×1.4×1.15×1.1  Formula (3):tbest=ttyp×0.6×0.85×0.9  Formula (4):
The quality of an LSI can be safely secured by excessively setting a design margin for the LSI, but although it is thus safely secured, the circuit design may become wasteful on the contrary. For example, since an excessive margin increases the circuit scale, the performance such as the operation frequency of the LSI is lowered. Accordingly, without a technique to evaluate not excessive but appropriate design margin and to design an LSI on the basis of the evaluated design margin, it is difficult to efficiently develop an optimum LSI, such as a recent digital signal processor, satisfactory in both the performance and the quality.
However, it is not easy to set an appropriate design margin against the fabrication variation because the occurrence mechanism of the fabrication variation is complicated. Specifically, the variation derived from the voltage or the temperature can be set on the basis of response of a circuit to one variable while there are a large number of variables (process variables) for determining the fabrication variation, and therefore, it is difficult to set a design margin against the fabrication variation. Therefore, a method for setting a design margin for an LSI as shown in FIG. 21 has been conventionally employed. Now, this method will be described in detail.
FIG. 21 is a flowchart for showing procedures in the conventional method for setting a design margin for an LSI.
Also, FIG. 22 is a table for showing variation ranges of process variables determined in a corner condition setting step S14 of the conventional method for setting a design margin for an LSI.
As shown in FIG. 21, in a test chip design step S10, a test chip of an LSI to be fabricated is first designed.
Next, in a test chip prototype step S11, the test chip designed in the test chip design step S10 is fabricated.
Then, in a test chip evaluation step S12, as a characteristic (a standard characteristic) used as a standard of an element (such as a transistor) included in the test chip fabricated in the test chip prototype step S11, and for example, as the standard characteristic of a transistor, a voltage-current characteristic of the transistor is measured.
Next, in a standard parameter extraction step S13, on the basis of the standard characteristic of the test chip measured in the test chip evaluation step S12, a standard value of a SPICE (Simulation Program with Integrated Circuit Emphasis) parameter set to be used in a circuit simulation step S15 described below is extracted.
Then, in a corner condition setting step S14, the range (variation range) within which the SPICE parameter set extracted in the standard parameter extraction step S13 is allowed to vary during the fabrication process is determined. Specifically, on the basis of variation specifications 20 for specifying the variation ranges of process variables during the fabrication process, the variation ranges of the process variables, such as a gate length, a threshold voltage and a gate oxide film thickness, derived from the fabrication variation are determined as shown in FIG. 22.
FIG. 22 shows examples of the variation ranges of the process variables determined on the basis of the variation specifications 20.
As shown in FIG. 22, on the basis of the variation specifications 20, the variation ranges, namely, the minimum values (listed in the column of “min”) and the maximum values (listed in the column of “max”) of the respective process variables, such as the gate length, the threshold voltage and the gate oxide film thickness, derived from the fabrication variation can be determined. When these variation ranges of the process variables are made to influence the standard value of the SPICE parameter obtained on the basis of the standard characteristic of the transistor, a corner condition, namely, the minimum value and the maximum value, of the SPICE parameter can be obtained. In general, in the corner condition of the SPICE parameter determined on the basis of the variation specifications 20, as the maximum value (namely, the upper limit), a value obtained by subtracting a triple value of a standard deviation σ from a standard value μ of the variation range of the process variable is selected. On the other hand, as the minimum value (lower limit) of the corner condition, a value obtained by adding the triple of the standard deviation σ to the standard value μ of the variation range of the process variable is selected.
Next, in the circuit simulation step S15, circuit simulation is performed by using a simple circuit model 21 by employing the standard value of the SPICE parameter and the corner condition. Specific procedures in this step are shown in FIG. 23.
FIG. 23 is a diagram for showing, in detail, the circuit simulation step S15 of FIG. 21 and an LSI delay variation prediction step S16 performed thereafter.
As shown in FIG. 23, the circuit simulation step S15 specifically includes a standard SPICE simulation step S15a and a slow SPICE simulation step S15b. In the standard SPICE simulation step S15a, the SPICE simulation is performed by using the standard value of the SPICE parameter (that is, a standard SPICE parameter), so as to calculate a standard delay time ta. On the contrary, in the slow SPICE simulation step S15b, the SPICE simulation is performed by using the maximum value of the corner condition of the SPICE parameter (that is, a slow SPICE parameter), so as to calculate a worst delay time tb. For this purpose, as a net list obtained on the assumption of a simple two-input NAND (2NAND) as the circuit model, a standard net list is prepared for the standard SPICE simulation step S15a, and a slow net list is prepared for the slow SPICE simulation step S15b. 
Furthermore, as shown in FIG. 23, the LSI delay variation prediction step S16 specifically includes a derating factor calculation step S16′. In the derating factor calculation step S16′, shift of the worst standard time tb calculated in the slow SPICE simulation step S15b from the standard delay time ta calculated in the standard SPICE simulation step S15a is calculated by using the following formula (5):P={(worst delay time)/(standard delay time)}≧1  Formula (5):
A delay variation ratio thus calculated corresponds to the derating factor P indicating, in the form of a coefficient, the fabrication variation as the delay varying factor. Specifically, the derating factor P thus calculated is set as the design margin against the fabrication variation of the LSI.
As described so far, in the conventional method for setting a design margin for an LSI, the standard SPICE parameter to be used in the circuit simulation is extracted on the basis of the standard characteristic of the transistor measured by using the test chip of the LSI, and the corner condition of the extracted SPICE parameter is determined on the basis of the variation specifications 20 of the general process variables. Also, the response of the circuit delay is obtained through the circuit simulation by using the corner condition of the SPICE parameter determined on the basis of the variation specifications 20 of the process variables, and the derating factor calculated on the basis of the circuit delay is set as the design margin.
However, in the conventional method for setting a design margin for an LSI, since the corner condition (the upper and lower limits) of the SPICE parameter to be used in the SPICE simulation is determined on the basis of the variation specifications 20 of the process variables shown in FIG. 22, a combination of specification values actually minimally possible is used. For example, the upper limit of the corner condition of the SPICE parameter corresponds to a combination of the maximum values (max) of all of the gate length, the threshold voltage and the gate oxide film thickness shown in FIG. 22. However, there is very small probability that these process variations are simultaneously the maximum, and hence, such a combination is actually minimally possible. Thus, in the conventional method, the SPICE simulation is performed by using the SPICE parameter having such an unrealistic corner condition. Therefore, the derating factor calculated on the basis of the delay time calculated through the SPICE simulation tends to have an excessive value. In other words, in the conventional method, an excessive design margin tends to be set. Also, since the circuit model 21 used in the circuit simulation step S15 is set as a simple model as shown in FIG. 23, it cannot be said that the current model is influenced by the actual features of the LSI. Therefore, the design margin set by the conventional method may have an excessive or insufficient value.